1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically writable and erasable semiconductor nonvolatile memory (EEPROM: Electrically Erasable and Programmable Read Only Memory).
2. Description of the Related Art
In recent years, there has rapidly spread a small semiconductor device with multiple functions and high performance, which is represented by a mobile appliance such as a mobile computer or a mobile phone. Accordingly, a semiconductor nonvolatile memory has been noted as a memory included in a semiconductor device. The semiconductor nonvolatile memory is characteristically superior in integration density, shock resistance, power consumption, writing/reading speed, or the like while it is inferior in storage capacity, to a magnetic disk. In recent years, there has been developed a semiconductor nonvolatile memory which has sufficient performance of the frequency of rewriting data and the time period for holding data, that had been problems of the semiconductor nonvolatile memory, and there has been a trend to employ the semiconductor nonvolatile memory in place of the magnetic disk.
Semiconductor nonvolatile memories are roughly classified into two classes: a full-function EEPROM and a flash memory. A full-function EEPROM is a semiconductor nonvolatile memory which is capable of erasing data for each bit, and can perform writing, reading, and erasing operations for each bit. The full-function EEPROM has higher functions while it is inferior in integration degree and cost as compared to the flash memory. On the other hand, a flash memory is a semiconductor nonvolatile memory for erasing all data of the memory in a batch or erasing data for each block unit of the memory, thereby realizing high integration density and low cost while giving up an erasing operation for each bit.
In the case of the flash memory, all data is necessarily erased to rewrite data for one bit. This makes the power consumption larger than that of the full-function EEPROM and lowers the reliability because data is rewritten even in a memory cell where data rewriting is not needed. Of course, the flash memory cannot be used for an application that needs an erasing operation for each bit.
Here, a full-function EEPROM is taken as an example of a conventional semiconductor nonvolatile memory, and a circuit diagram thereof and a cross-sectional view and a driving method of a memory cell thereof are described.
FIG. 12 is a circuit diagram of a conventional full-function EEPROM. The full-function EEPROM shown in FIG. 12 includes a memory cell array 405 in which a plurality of memory cells (1, 1) to (m, n) are arranged in matrix so as to be m memory cells in column and n memory cells in row, an X address decoder 401, a Y address decoder 402, and other peripheral circuits 403 and 404.
Each memory cell (typically, a memory cell (i, j) is considered) (i is an integer which is greater than or equal to 1 and less than or equal to m, and j is an integer which is greater than or equal to 1 and less than or equal to n) includes an n-channel memory transistor Tr1 and an n-channel selection transistor Tr2. The two transistors are connected in series. A source electrode and a control gate electrode of the memory transistor Tr1 are connected to a source line Si and a word line Wj, respectively. A drain electrode and a gate electrode of the selection transistor Tr2 are connected to a bit line Bi and a selection line Vj, respectively. Further, bit lines B1 to Bn are connected to the Y address decoder 402, and word lines W1 and Wm and selection lines V1 to Vm are connected to the X address decoder 401. A predetermined potential Vs is applied to source lines S1 to Sn in common.
In the case where 1-bit data is stored in each memory transistor included in each memory cell, the full-function EEPROM shown in FIG. 12 has storage capacity of m×n bits.
However, the full-function EEPROM has a problem in that a memory cell area is large and the integration density is low because each memory cell in which 1-bit data is stored includes two transistors, that are the memory transistor and the selection transistor. This obstructs reduction in size and cost of the full-function EEPROM.
For solving the above-described problem, a structure for improving the integration density by providing one more memory transistor instead of a selection transistor in each memory cell in which 1-bit data is stored, and the like have been proposed (e.g., Japanese Published Patent Application No. 2002-43447). Further, in recent years, a memory element has been utilized in various fields, and smaller and mobile nonvolatile memory having large capacity has been demanded.